Cerebras Built a Chip the Size of a Dinner Plate Because Memory Is the Wall

Most AI chips spend a lot of their time waiting. The math units sit idle while the memory system hauls in the next slab of model weights, and that waiting is a big part of why a chatbot pauses before it answers you. Cerebras's answer has been to skip the step where a wafer gets cut into individual chips and ship the entire wafer as one processor.

That wafer is close to the size of a dinner plate: 46,225 square millimeters, a bit under 8.5 inches on a side, carrying four trillion transistors and 900,000 cores. Cerebras announced the CS-4 in mid-August, a rack holding three of them, with first shipments beginning this quarter. At Hot Chips this week the company walked through how the rack is built and where the wafer goes next.

Nexus is the rack, not the chip

Cerebras designed Nexus as a reusable frame. Power comes in the front, and the compute slides into the back as self-contained "backpacks," each carrying its own power delivery, cooling and I/O. Cerebras says the design uses about half the components of the CS-3, and that the same rack will carry the CS-4, CS-5 and CS-6 in turn, so a new wafer doesn't force a new rack.

The power delivery is the clever bit. Cerebras puts its AC/DC conversion half a millimeter from the wafer, against about 50 millimeters in a GPU system, and feeds the wafer through a copper busbar rather than through a circuit board. Chief system architect JP Fricker spent part of his talk contrasting that with the 5,000 or so cables in Nvidia's Rubin NVLink scale-up domain, which he called "a mess."

The chip inside is an overclock

The WSE-3 Turbo in the CS-4 is the WSE-3 that was already shipping. Same four trillion transistors, same 900,000 cores, same 44GB of on-wafer SRAM, same TSMC 5nm process. What changed is the clock, from about 1.4GHz to about 2.8GHz, which doubles the per-wafer figures across the board. Putting three wafers in a rack instead of one does the rest, and gives Cerebras three times the compute per rack it had with the CS-3.

Per rack, Cerebras quotes 750 petaflops of sparse FP16 compute, 132GB of SRAM, 129.6 petabytes per second of memory bandwidth, 160.5 petabytes per second of on-chip fabric bandwidth, 7.2 terabits per second of system I/O, and two microseconds of wafer-to-wafer latency.

About that 30x

Cerebras says the CS-4 runs frontier models up to 30 times faster than GPU-based systems, up to twice as fast as the CS-3, and with up to 10 times the throughput per watt. The 30x is tokens per second per user on a single model, gpt-oss-120b, where Cerebras measured more than 4,400 tokens per second per user, against GPU systems it doesn't name. The company's own footnote says throughput varies by model architecture, context length, precision and serving configuration, and The Next Web pointed out that the comparison sets Cerebras's sparse FP16 numbers against dense ones.

Cerebras also claims about 200 times the scale-up bandwidth of an Nvidia Rubin NVL72 rack, 53.5 petabytes per second of on-wafer fabric per wafer against 260 terabytes per second. That pits an on-die fabric against a rack full of cables, which is either the entire point or an unfair fight, depending on how much you like the wafer idea.

Buyers here aren't chasing a cheaper flop. CTO Sean Lie made the pitch on latency: "Being 30 times faster doesn't just make a response feel fast. It gives an agentic system room for more than an order of magnitude as much reasoning, verification, or tool use in the same wall-clock time." If you're running agents that make dozens of model calls before a person sees anything, that compounding is the sale. If you're training rather than serving, this isn't aimed at you.

Memory is the wall

All 44GB on a wafer is SRAM, sitting on the wafer itself, which is where the 43.2 petabytes per second of per-wafer memory bandwidth comes from. Nothing goes off-chip to fetch weights. The catch is capacity. 44GB per wafer and 132GB per rack aren't much when frontier models run to trillions of parameters, so a large model gets spread across a lot of wafers.

There's also nowhere left to put more of it. Cerebras's framing at Hot Chips was that the wafer's area is already 100 percent used by logic and memory. More SRAM means fewer cores. That constraint is the reason the roadmap looks the way it does.

What's a product and what's a slide

The CS-5 is set for 2027 and will use new WSE silicon. Cerebras is targeting up to 10,000 output tokens per second per user on smaller open models such as Gemma 4 31B and gpt-oss-120b, up to 5,000 per user on frontier models, and 3 million tokens per second per megawatt. CEO Andrew Feldman has said he expects the company to be four times faster with 20 times more throughput by the end of 2027. Those are targets, not measurements.

The CS-6 sits further out, described only as two generations away. The memory fix is supposed to land there, with DRAM stacked in 3D on top of the compute and SRAM wafer, joined by very high bandwidth vertical connections, so capacity can grow without weights having to travel any real distance. The coverage muddles which memory that is. Wccftech's write-up has the CS-6 adding wafer-scale SRAM through 3D integration. Cerebras's own deep dive says DRAM, layered onto the wafer-scale SRAM and compute that's already there.

Cerebras put no date on the CS-6. What ships this quarter is a rack of three overclocked wafers, sold on the bet that feeding the math is harder than doing it. Everything past that is a slide deck.